#MCell 4.20 #GAME Rules table #RULE 1,0,0,0,0,0,0,0,0,0,0,0,0,2,2,2,2,2,2,2,2,2,0,3,3,3,3,3,3,3,3,3, #RULE 0,3,1,1,3,3,3,3,3,3 #BOARD 400x200 #WRAP 0 #CCOLORS 4 #D Design by Nyles Heise (nylesheise@yahoo.com). Previous multipliers #D by Nick Gardner and Karl Scherer. #D #D This is 32-bit by 32-bit binary muliplier producing a 64 bit product. #D Two versions are given. The compact version is crammed into the #D minimum area I could get to (you may be able to do better). The #D expanded version has the component separated and labeled, to give a #D better view of what's going on. #D #D A is the multiplicand, 252 cells. B is the multiplier, 124 cells. #D C is the product, 256 cells in the expanded version. FA is a single #D full adder. Gate is used to gate the bits of A into FA when the #D corresponding bit of B was on. Also turns off the B bit after it #D has been used. Clock tells Gate when to look at B. It's a fill-empty #D ring counter, 128 cells and a period of 252 cycles. #D The first partial result appears in the expanded verion in C after #D 205 cycles, next in another 256, and so on. Final product in a total #D of 8141 cycles. 8116 is the compact verion, some bits always in the FA. #D #D The design uses 4-tick logic elements. 6-tick takes 50% more space for #D the loops and 50% more overall time. All the normal logic elements #D are available in 4-tick (OR, XOR, AND, INVERT, R-S LATCH, T LATCH). #D The 4-tick INVERTER is shown bottom left. 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